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a.out.h
7.15
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acct.h
3.58
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adb.h
1.05
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adfs_fs.h
873
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affs_hardblocks.h
1.45
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agpgart.h
3.83
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aio_abi.h
3.1
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apm_bios.h
3.46
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arcfb.h
150
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atalk.h
960
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atm.h
7.64
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atm_eni.h
585
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atm_he.h
343
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atm_idt77105.h
892
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atm_nicstar.h
1.19
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atm_tcp.h
1.52
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atm_zatm.h
1.57
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atmapi.h
889
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atmarp.h
1.2
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atmbr2684.h
3.13
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atmclip.h
513
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atmdev.h
7.44
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atmioc.h
1.55
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atmlec.h
2.26
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atmmpc.h
4.07
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atmppp.h
576
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atmsap.h
4.79
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atmsvc.h
1.75
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audit.h
18.03
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auto_fs.h
2.53
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auto_fs4.h
4.3
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auxvec.h
1.4
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ax25.h
2.7
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b1lli.h
1.62
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baycom.h
820
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bfs_fs.h
1.79
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binfmts.h
565
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blkpg.h
1.53
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blktrace_api.h
4.38
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bpf.h
22.04
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bpf_common.h
1.2
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bpf_perf_event.h
453
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bpqether.h
952
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bsg.h
2.37
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bt-bmc.h
508
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btrfs.h
25.07
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can.h
5.46
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capability.h
11.25
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capi.h
2.99
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cciss_defs.h
3.14
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cciss_ioctl.h
2.63
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cdrom.h
28.12
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cgroupstats.h
2.1
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chio.h
5.16
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cm4000_cs.h
1.68
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cn_proc.h
3.19
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coda.h
17.09
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coda_psdev.h
720
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coff.h
12.12
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connector.h
2.14
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const.h
673
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cramfs_fs.h
2.68
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cuda.h
842
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cyclades.h
16.65
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cycx_cfm.h
2.86
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dcbnl.h
24.5
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dccp.h
6.22
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devlink.h
9.66
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dlm.h
2.43
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dlm_device.h
2.42
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dlm_netlink.h
1.04
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dlm_plock.h
831
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dlmconstants.h
4.9
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dm-ioctl.h
10.55
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dm-log-userspace.h
14.82
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dn.h
4.42
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dqblk_xfs.h
8.72
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edd.h
5.41
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efs_fs_sb.h
2.11
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elf-em.h
1.83
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elf-fdpic.h
1.04
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elf.h
12.69
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elfcore.h
2.86
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errno.h
23
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errqueue.h
1.1
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ethtool.h
71.11
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eventpoll.h
1.76
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fadvise.h
779
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falloc.h
2.72
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fanotify.h
3.52
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fb.h
16
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fcntl.h
2.16
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fd.h
11.31
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fdreg.h
5.23
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fib_rules.h
1.58
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fiemap.h
2.65
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filter.h
1.99
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firewire-cdev.h
42.86
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firewire-constants.h
3.16
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flat.h
2.04
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fou.h
617
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fs.h
8.47
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fsl_hypervisor.h
7.05
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fuse.h
16.41
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futex.h
4.81
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gameport.h
834
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gen_stats.h
1.5
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genetlink.h
1.82
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gfs2_ondisk.h
12
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gigaset_dev.h
1.35
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hdlc.h
574
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hdlcdrv.h
2.78
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hdreg.h
22.11
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hid.h
1.79
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hiddev.h
6.13
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hidraw.h
1.41
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hpet.h
680
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hw_breakpoint.h
679
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hyperv.h
10.22
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hysdn_if.h
1.29
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i2c-dev.h
2.37
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i2c.h
6.66
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i2o-dev.h
11.22
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i8k.h
1.4
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icmp.h
2.82
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icmpv6.h
3.82
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if.h
9.26
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if_addr.h
1.7
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if_addrlabel.h
658
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if_alg.h
816
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if_arcnet.h
3.63
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if_arp.h
6.3
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if_bonding.h
4.66
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if_bridge.h
6.46
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if_cablemodem.h
922
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if_eql.h
1.26
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if_ether.h
7.25
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if_fc.h
1.63
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if_fddi.h
3.6
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if_frad.h
2.89
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if_hippi.h
4.07
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if_infiniband.h
1.13
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if_link.h
19.58
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if_ltalk.h
147
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if_macsec.h
5.42
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if_packet.h
7.15
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if_phonet.h
361
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if_plip.h
596
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if_ppp.h
29
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if_pppol2tp.h
3.18
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if_pppox.h
4.64
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if_slip.h
809
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if_team.h
2.48
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if_tun.h
3.71
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if_tunnel.h
3.03
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if_vlan.h
1.69
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if_x25.h
817
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ife.h
288
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igmp.h
2.88
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in.h
9.36
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in6.h
6.97
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in_route.h
873
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inet_diag.h
2.77
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inotify.h
2.85
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input.h
32.52
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ioctl.h
100
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ip.h
3.47
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ip6_tunnel.h
1.67
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ip_vs.h
12.77
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ipc.h
1.99
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ipmi.h
14.63
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ipmi_msgdefs.h
3.21
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ipsec.h
884
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ipv6.h
3.66
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ipv6_route.h
1.73
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ipx.h
1.79
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irda.h
7.31
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irqnr.h
104
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isdn.h
5.58
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isdn_divertif.h
1.11
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isdn_ppp.h
1.82
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isdnif.h
2.25
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iso_fs.h
6.29
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ivtv.h
2.89
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ivtvfb.h
1.12
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ixjuser.h
24.53
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jffs2.h
6.85
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joystick.h
3.5
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kd.h
6.04
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kdev_t.h
320
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kernel-page-flags.h
788
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kernel.h
375
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kernelcapi.h
956
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kexec.h
1.92
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keyboard.h
12.42
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keyctl.h
2.98
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kvm.h
33.89
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kvm_para.h
819
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l2tp.h
4.98
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libc-compat.h
4.03
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limits.h
874
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llc.h
2.98
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loop.h
2.31
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lp.h
3.72
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lwtunnel.h
839
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magic.h
2.9
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major.h
4.48
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map_to_7segment.h
7.02
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matroxfb.h
1.37
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mdio.h
13.74
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media.h
3.5
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mei.h
4.62
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membarrier.h
7.71
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memfd.h
186
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mempolicy.h
2.35
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meye.h
2.41
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mii.h
7.76
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minix_fs.h
2.01
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mman.h
230
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mmtimer.h
2.01
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mpls.h
1.33
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mqueue.h
2.01
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mroute.h
4.06
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mroute6.h
4.08
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msdos_fs.h
6.28
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msg.h
3.21
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mtio.h
7.92
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n_r3964.h
2.29
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nbd.h
2.34
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ncp.h
4.94
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ncp_fs.h
3.27
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ncp_mount.h
2.06
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ncp_no.h
651
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ndctl.h
6.6
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neighbour.h
4.17
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net.h
1.97
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net_dropmon.h
1.07
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net_namespace.h
609
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net_tstamp.h
4.06
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netconf.h
423
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netdevice.h
1.46
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netfilter.h
1.6
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netfilter_arp.h
380
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netfilter_bridge.h
768
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netfilter_decnet.h
1.83
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netfilter_ipv4.h
2.02
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netfilter_ipv6.h
2.04
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netlink.h
6.13
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netlink_diag.h
1005
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netrom.h
744
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nfc.h
7.72
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nfs.h
4.31
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nfs2.h
1.37
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nfs3.h
2.24
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nfs4.h
5.95
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nfs4_mount.h
1.83
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nfs_fs.h
1.51
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nfs_idmap.h
2.19
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nfs_mount.h
2.32
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nfsacl.h
605
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nl80211.h
270.89
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nubus.h
8.17
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nvme_ioctl.h
1.55
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nvram.h
469
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omap3isp.h
20.19
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omapfb.h
5.72
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oom.h
448
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openvswitch.h
31.79
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packet_diag.h
1.5
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param.h
78
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parport.h
3.56
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patchkey.h
829
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pci.h
1.29
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pci_regs.h
50.79
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perf_event.h
31.96
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personality.h
1.99
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pfkeyv2.h
9.91
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pg.h
2.23
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phantom.h
1.55
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phonet.h
4.51
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pkt_cls.h
12.49
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pkt_sched.h
20.63
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pktcdvd.h
2.56
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pmu.h
5.13
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poll.h
22
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posix_types.h
1.01
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ppdev.h
3.07
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ppp-comp.h
2.41
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ppp-ioctl.h
5.29
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ppp_defs.h
4.93
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pps.h
4.06
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prctl.h
6.75
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psample.h
735
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ptp_clock.h
5.09
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ptrace.h
3.08
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qnx4_fs.h
2.21
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qnxtypes.h
561
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quota.h
5.78
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radeonfb.h
297
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random.h
1.2
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raw.h
302
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rds.h
7.9
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reboot.h
1.25
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reiserfs_fs.h
712
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reiserfs_xattr.h
470
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resource.h
2.09
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rfkill.h
3.5
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romfs_fs.h
1.15
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rose.h
2.12
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route.h
2.21
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rtc.h
3.85
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rtnetlink.h
17.02
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scc.h
4.43
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sched.h
2.26
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screen_info.h
2.36
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sctp.h
29.53
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sdla.h
2.71
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seccomp.h
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Code Editor : v4l2-dv-timings.h
/* * V4L2 DV timings header. * * Copyright (C) 2012 Hans Verkuil <hans.verkuil@cisco.com> * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * version 2 as published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, but * WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA * 02110-1301 USA */ #ifndef _V4L2_DV_TIMINGS_H #define _V4L2_DV_TIMINGS_H #if __GNUC__ < 4 || (__GNUC__ == 4 && (__GNUC_MINOR__ < 6)) /* Sadly gcc versions older than 4.6 have a bug in how they initialize anonymous unions where they require additional curly brackets. This violates the C1x standard. This workaround adds the curly brackets if needed. */ #define V4L2_INIT_BT_TIMINGS(_width, args...) \ { .bt = { _width , ## args } } #else #define V4L2_INIT_BT_TIMINGS(_width, args...) \ .bt = { _width , ## args } #endif /* CEA-861-E timings (i.e. standard HDTV timings) */ #define V4L2_DV_BT_CEA_640X480P59_94 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \ 25175000, 16, 96, 48, 10, 2, 33, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, 0) \ } /* Note: these are the nominal timings, for HDMI links this format is typically * double-clocked to meet the minimum pixelclock requirements. */ #define V4L2_DV_BT_CEA_720X480I59_94 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(720, 480, 1, 0, \ 13500000, 19, 62, 57, 4, 3, 15, 4, 3, 16, \ V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_HALF_LINE) \ } #define V4L2_DV_BT_CEA_720X480P59_94 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(720, 480, 0, 0, \ 27000000, 16, 62, 60, 9, 6, 30, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, 0) \ } /* Note: these are the nominal timings, for HDMI links this format is typically * double-clocked to meet the minimum pixelclock requirements. */ #define V4L2_DV_BT_CEA_720X576I50 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(720, 576, 1, 0, \ 13500000, 12, 63, 69, 2, 3, 19, 2, 3, 20, \ V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_HALF_LINE) \ } #define V4L2_DV_BT_CEA_720X576P50 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(720, 576, 0, 0, \ 27000000, 12, 64, 68, 5, 5, 39, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, 0) \ } #define V4L2_DV_BT_CEA_1280X720P24 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 720, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 59400000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, \ V4L2_DV_FL_CAN_REDUCE_FPS) \ } #define V4L2_DV_BT_CEA_1280X720P25 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 720, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 74250000, 2420, 40, 220, 5, 5, 20, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, 0) \ } #define V4L2_DV_BT_CEA_1280X720P30 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 720, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 74250000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \ } #define V4L2_DV_BT_CEA_1280X720P50 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 720, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 74250000, 440, 40, 220, 5, 5, 20, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, 0) \ } #define V4L2_DV_BT_CEA_1280X720P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 720, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 74250000, 110, 40, 220, 5, 5, 20, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \ } #define V4L2_DV_BT_CEA_1920X1080P24 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 74250000, 638, 44, 148, 4, 5, 36, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \ } #define V4L2_DV_BT_CEA_1920X1080P25 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 74250000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, 0) \ } #define V4L2_DV_BT_CEA_1920X1080P30 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 74250000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \ } #define V4L2_DV_BT_CEA_1920X1080I50 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 74250000, 528, 44, 148, 2, 5, 15, 2, 5, 16, \ V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_HALF_LINE) \ } #define V4L2_DV_BT_CEA_1920X1080P50 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 148500000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, 0) \ } #define V4L2_DV_BT_CEA_1920X1080I60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 74250000, 88, 44, 148, 2, 5, 15, 2, 5, 16, \ V4L2_DV_BT_STD_CEA861, \ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_HALF_LINE) \ } #define V4L2_DV_BT_CEA_1920X1080P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 148500000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, \ V4L2_DV_FL_CAN_REDUCE_FPS) \ } /* VESA Discrete Monitor Timings as per version 1.0, revision 12 */ #define V4L2_DV_BT_DMT_640X350P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(640, 350, 0, V4L2_DV_HSYNC_POS_POL, \ 31500000, 32, 64, 96, 32, 3, 60, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_640X400P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(640, 400, 0, V4L2_DV_VSYNC_POS_POL, \ 31500000, 32, 64, 96, 1, 3, 41, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_720X400P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(720, 400, 0, V4L2_DV_VSYNC_POS_POL, \ 35500000, 36, 72, 108, 1, 3, 42, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } /* VGA resolutions */ #define V4L2_DV_BT_DMT_640X480P60 V4L2_DV_BT_CEA_640X480P59_94 #define V4L2_DV_BT_DMT_640X480P72 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \ 31500000, 24, 40, 128, 9, 3, 28, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_640X480P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \ 31500000, 16, 64, 120, 1, 3, 16, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_640X480P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \ 36000000, 56, 56, 80, 1, 3, 25, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } /* SVGA resolutions */ #define V4L2_DV_BT_DMT_800X600P56 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(800, 600, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 36000000, 24, 72, 128, 1, 2, 22, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_800X600P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(800, 600, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 40000000, 40, 128, 88, 1, 4, 23, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_800X600P72 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(800, 600, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 50000000, 56, 120, 64, 37, 6, 23, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_800X600P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(800, 600, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 49500000, 16, 80, 160, 1, 3, 21, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_800X600P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(800, 600, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 56250000, 32, 64, 152, 1, 3, 27, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_800X600P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(800, 600, 0, V4L2_DV_HSYNC_POS_POL, \ 73250000, 48, 32, 80, 3, 4, 29, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_848X480P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(848, 480, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 33750000, 16, 112, 112, 6, 8, 23, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1024X768I43 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1024, 768, 1, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 44900000, 8, 176, 56, 0, 4, 20, 0, 4, 21, \ V4L2_DV_BT_STD_DMT, 0) \ } /* XGA resolutions */ #define V4L2_DV_BT_DMT_1024X768P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1024, 768, 0, 0, \ 65000000, 24, 136, 160, 3, 6, 29, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1024X768P70 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1024, 768, 0, 0, \ 75000000, 24, 136, 144, 3, 6, 29, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1024X768P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1024, 768, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 78750000, 16, 96, 176, 1, 3, 28, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1024X768P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1024, 768, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 94500000, 48, 96, 208, 1, 3, 36, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1024X768P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1024, 768, 0, V4L2_DV_HSYNC_POS_POL, \ 115500000, 48, 32, 80, 3, 4, 38, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } /* XGA+ resolution */ #define V4L2_DV_BT_DMT_1152X864P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1152, 864, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 108000000, 64, 128, 256, 1, 3, 32, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1280X720P60 V4L2_DV_BT_CEA_1280X720P60 /* WXGA resolutions */ #define V4L2_DV_BT_DMT_1280X768P60_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_HSYNC_POS_POL, \ 68250000, 48, 32, 80, 3, 7, 12, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1280X768P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \ 79500000, 64, 128, 192, 3, 7, 20, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1280X768P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \ 102250000, 80, 128, 208, 3, 7, 27, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1280X768P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \ 117500000, 80, 136, 216, 3, 7, 31, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1280X768P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_HSYNC_POS_POL, \ 140250000, 48, 32, 80, 3, 7, 35, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1280X800P60_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, \ 71000000, 48, 32, 80, 3, 6, 14, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1280X800P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \ 83500000, 72, 128, 200, 3, 6, 22, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1280X800P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \ 106500000, 80, 128, 208, 3, 6, 29, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1280X800P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \ 122500000, 80, 136, 216, 3, 6, 34, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1280X800P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, \ 146250000, 48, 32, 80, 3, 6, 38, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1280X960P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 960, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 108000000, 96, 112, 312, 1, 3, 36, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1280X960P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 960, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 148500000, 64, 160, 224, 1, 3, 47, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1280X960P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 960, 0, V4L2_DV_HSYNC_POS_POL, \ 175500000, 48, 32, 80, 3, 4, 50, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } /* SXGA resolutions */ #define V4L2_DV_BT_DMT_1280X1024P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 108000000, 48, 112, 248, 1, 3, 38, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1280X1024P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 135000000, 16, 144, 248, 1, 3, 38, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1280X1024P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 157500000, 64, 160, 224, 1, 3, 44, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1280X1024P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 1024, 0, V4L2_DV_HSYNC_POS_POL, \ 187250000, 48, 32, 80, 3, 7, 50, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1360X768P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1360, 768, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 85500000, 64, 112, 256, 3, 6, 18, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1360X768P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1360, 768, 0, V4L2_DV_HSYNC_POS_POL, \ 148250000, 48, 32, 80, 3, 5, 37, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1366X768P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1366, 768, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 85500000, 70, 143, 213, 3, 3, 24, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1366X768P60_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1366, 768, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 72000000, 14, 56, 64, 1, 3, 28, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \ } /* SXGA+ resolutions */ #define V4L2_DV_BT_DMT_1400X1050P60_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_HSYNC_POS_POL, \ 101000000, 48, 32, 80, 3, 4, 23, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1400X1050P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \ 121750000, 88, 144, 232, 3, 4, 32, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1400X1050P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \ 156000000, 104, 144, 248, 3, 4, 42, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1400X1050P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \ 179500000, 104, 152, 256, 3, 4, 48, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1400X1050P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_HSYNC_POS_POL, \ 208000000, 48, 32, 80, 3, 4, 55, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } /* WXGA+ resolutions */ #define V4L2_DV_BT_DMT_1440X900P60_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_HSYNC_POS_POL, \ 88750000, 48, 32, 80, 3, 6, 17, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1440X900P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \ 106500000, 80, 152, 232, 3, 6, 25, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1440X900P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \ 136750000, 96, 152, 248, 3, 6, 33, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1440X900P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \ 157000000, 104, 152, 256, 3, 6, 39, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1440X900P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_HSYNC_POS_POL, \ 182750000, 48, 32, 80, 3, 6, 44, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1600X900P60_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1600, 900, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 108000000, 24, 80, 96, 1, 3, 96, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \ } /* UXGA resolutions */ #define V4L2_DV_BT_DMT_1600X1200P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 162000000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1600X1200P65 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 175500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1600X1200P70 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 189000000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1600X1200P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 202500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1600X1200P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 229500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1600X1200P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1600, 1200, 0, V4L2_DV_HSYNC_POS_POL, \ 268250000, 48, 32, 80, 3, 4, 64, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } /* WSXGA+ resolutions */ #define V4L2_DV_BT_DMT_1680X1050P60_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_HSYNC_POS_POL, \ 119000000, 48, 32, 80, 3, 6, 21, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1680X1050P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \ 146250000, 104, 176, 280, 3, 6, 30, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1680X1050P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \ 187000000, 120, 176, 296, 3, 6, 40, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1680X1050P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \ 214750000, 128, 176, 304, 3, 6, 46, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1680X1050P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_HSYNC_POS_POL, \ 245500000, 48, 32, 80, 3, 6, 53, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1792X1344P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_VSYNC_POS_POL, \ 204750000, 128, 200, 328, 1, 3, 46, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1792X1344P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_VSYNC_POS_POL, \ 261000000, 96, 216, 352, 1, 3, 69, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1792X1344P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_HSYNC_POS_POL, \ 333250000, 48, 32, 80, 3, 4, 72, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1856X1392P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_VSYNC_POS_POL, \ 218250000, 96, 224, 352, 1, 3, 43, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1856X1392P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_VSYNC_POS_POL, \ 288000000, 128, 224, 352, 1, 3, 104, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1856X1392P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_HSYNC_POS_POL, \ 356500000, 48, 32, 80, 3, 4, 75, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1920X1080P60 V4L2_DV_BT_CEA_1920X1080P60 /* WUXGA resolutions */ #define V4L2_DV_BT_DMT_1920X1200P60_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_HSYNC_POS_POL, \ 154000000, 48, 32, 80, 3, 6, 26, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1920X1200P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \ 193250000, 136, 200, 336, 3, 6, 36, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1920X1200P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \ 245250000, 136, 208, 344, 3, 6, 46, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1920X1200P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \ 281250000, 144, 208, 352, 3, 6, 53, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1920X1200P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_HSYNC_POS_POL, \ 317000000, 48, 32, 80, 3, 6, 62, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1920X1440P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_VSYNC_POS_POL, \ 234000000, 128, 208, 344, 1, 3, 56, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1920X1440P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_VSYNC_POS_POL, \ 297000000, 144, 224, 352, 1, 3, 56, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1920X1440P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_HSYNC_POS_POL, \ 380500000, 48, 32, 80, 3, 4, 78, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_2048X1152P60_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(2048, 1152, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 162000000, 26, 80, 96, 1, 3, 44, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \ } /* WQXGA resolutions */ #define V4L2_DV_BT_DMT_2560X1600P60_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_HSYNC_POS_POL, \ 268500000, 48, 32, 80, 3, 6, 37, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_2560X1600P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \ 348500000, 192, 280, 472, 3, 6, 49, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_2560X1600P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \ 443250000, 208, 280, 488, 3, 6, 63, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_2560X1600P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \ 505250000, 208, 280, 488, 3, 6, 73, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_2560X1600P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_HSYNC_POS_POL, \ 552750000, 48, 32, 80, 3, 6, 85, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1366X768P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1366, 768, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 85500000, 70, 143, 213, 3, 3, 24, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #endif
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